Wednesday, 15 July 2009

Adventures with VHDL part 1.

Well I've finally got my arse in gear and started playing around with VHDL. I am subjecting myself to this for two reasons: 1) being able to program firmware is cool and useful as well being a reasonably rare skill 2) it's going to be useful for my PhD.

So what am I doing I hear you cry? Firstly I have been lent a very fun piece of kit: a Digilent NEXYS 2 board this is a programmable board with all sorts of ports and switches LEDs and similar to play with. Attaching it to my pc is a basic USB cable and then I have the Xilinx WebPack (a free download containing IDE and other useful programming gubbins). The final thing needed was the digilent program 'Adept' which allows you to upload your program via USB.

Armed with these I have ventured forwards into the world of chip programming.

So what have I learnt? thus far not much, I've got a basic program running that depending on the configuration of 4 switches the 7-segment display will give the number converted from binary into hexadecimal this was done by follow thing this fairly basic tutorial.

I learnt two major things: firstly check the EXACT setting of your card. I had a lot of issues in that I was getting a "device IDCODE conflict" error every time I tried to load the program on to the hardware this was because I had it set for the XC3S500E not the XC3S1200E in the 'Design properties' (right click the any of the files in the 'design' pane). The second thing I learnt was that to set the start up clock you need to right click 'Generate Programming File' in the process pane.

This sort of programming is interesting it that everything has two entries into your code: the first is called the entity which describes the number of inputs and outputs to a given structure; the second is the architecture that actually describes what is to be done with those inputs and outputs.

In my case the inputs are the switches and the outputs are the 7Seg display as well as anodes which switch of the bits of the display that I don't want (there are 4 separate 7seg displays I need only one).

The architecture is where the interesting programming happens (as far as I can tell) with '<=' directing inputs to outputs. In this case 'select' was used select a binary string for controlling the 7seg when a certain value was input via the switches (x0 through to xE). The anodes were all set manually via the line 'anodes <= "1110"; ' (remember that for this '1' is off '0' is on) this was done so that only the right most display was on.

On the entity side ports (inputs/outputs) were declared as a block of '3 downto 0' giving ports 3,2,1,0. each being declared "STD_LOGIC_VECTOR" which I assume defines the arithmetic to which it subscribes.

Finally once your .hdl file is finished you need to declare what physical ports everything attaches to. This is via a .ucf file that simply translates the port from the VHDL file to an actual port (in this case by looking up the number on the board itself).

No comments: